Liquid crystal display

ABSTRACT

There is provided a liquid crystal display device in which the wiring resistivity of signal lines is reduced. The liquid crystal display device includes substrates disposed in opposition to each other with a liquid crystal interposed therebetween, a thin film transistor to be driven by a scanning signal supplied from a gate signal line, and a pixel electrode to be supplied with a video signal from a drain signal line via the thin film transistor, the thin film transistor and the pixel being provided in each pixel area on a liquid-crystal-side surface of one of the substrates. The gate signal line is made of a multi-layered structure including at least an ITO film formed on the liquid-crystal-side surface and a Mo layer formed to overlie the ITO film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a liquid crystal display device,and more particularly, to an active matrix type of liquid crystaldisplay device.

[0003] 2. Background Art

[0004] An active matrix type of liquid crystal display device includespixel areas provided on a liquid-crystal-side surface of either one ofsubstrates disposed in opposition to each other with a liquid crystalinterposed therebetween, each of the pixel areas being an areasurrounded by gate signal lines disposed to be extended in the xdirection and to be juxtaposed in the y direction and drain signal linesdisposed to be extended in the y direction and to be juxtaposed in the xdirection.

[0005] Each of the pixel areas includes a switching element to be drivenby a gate signal from either one of the gate signal lines, and a pixelelectrode to be supplied with a video signal from a drain signal linevia the switching element.

[0006] Two types of liquid crystal display devices are known. One is aso-called vertical electric field type of liquid crystal display devicein which a counter electrode common to each pixel area is formed on theliquid-crystal-side surface of one of substrates so that the opticaltransmissivity of its liquid crystal is controlled by an electric fieldgenerated between the counter electrode and a pixel electrodeapproximately perpendicularly to the substrates. The other is aso-called in-plane-switching type of liquid crystal display device inwhich a pixel electrode and an adjacent counter electrode are formed ineach pixel area on a substrate on which pixel electrodes are formed, sothat the optical transmissivity of its liquid crystal is controlled byan electric field generated between the pixel electrode and the counterelectrode approximately in parallel with the substrate.

[0007] However, it has been demanded that the gate signal lines or thedrain signal lines of such a liquid crystal display device have smallerwiring resistivity to cope with a recent increase in panel size.

[0008] In other words, by reducing the wiring resistivity of thesesignal lines, it is possible to restrain the delay of signals, wherebyit is possible to achieve far larger panel sizes.

[0009] However, even if the wiring resistivity of these signal lines canbe reduced, it is necessary to avoid an increase in the number ofmanufacturing processes because yield factor decreases.

[0010] In addition, in the case where a conductive layer, asemiconductor layer and an insulating layer are stacked in apredetermined pattern on a liquid-crystal-surface side of a substrate,the resultant steep steps are required to be made as smooth as possiblein terms of an improvement in the yield factor. This is because a filmundergoes climb-over damages in portions where the steps are present.

SUMMARY OF THE INVENTION

[0011] The invention has been made in view of the above-describedproblems, and one object of the invention is to provides a liquidcrystal display device in which the wiring resistivity of signal linesis small.

[0012] Another object of the invention is to provide a liquid crystaldisplay device in which few steep steps are present on aliquid-crystal-side surface of a substrate.

[0013] Another object of the invention is to provide a manufacturingmethod for a liquid crystal display device in which the number ofmanufacturing processes is made small.

[0014] Representative aspects of the invention disclosed in the presentapplication will be described below in brief.

[0015] A liquid crystal display device according to the inventionincludes: substrates disposed in opposition to each other with a liquidcrystal interposed therebetween; a thin film transistor to be driven bya scanning signal supplied from a gate signal line; and a pixelelectrode to be supplied with a video signal from a drain signal linevia the thin film transistor, the thin film transistor and the pixelbeing provided in each pixel area on a liquid-crystal-side surface ofone of the substrates. The gate signal line is made of a multi-layeredstructure including, for example, an ITO film formed on theliquid-crystal-side surface, and a Mo layer formed to overlie the ITOfilm.

[0016] In the liquid crystal display device constructed in this manner,the wiring resistivity of the gate signal lines is made small by usingMo or the like which has a small resistivity.

[0017] In this case, the reason why the ITO film or the like isinterposed between the Mo layer and the substrate is that if the gatesignal line is made of a single layer of Mo or the like, the adhesion ofthe gate signal line to the substrate becomes insufficient.

[0018] In the case where the gate signal line made of such multi-layeredstructure is formed by selective etching, the side walls of the gatesignal line are respectively formed to have tapered surfaces whichbecome gradually more open toward the substrate, whereby it is possibleto decrease steep steps.

[0019] A manufacturing method for a liquid crystal display deviceaccording to the invention includes the steps of: forming, on asubstrate, gate signal lines each made of a stacked structure in which atransparent conductive film and a metal layer are stacked in that order;forming an insulating film to cover the gate signal lines; forming, onthe insulating film, a stacked structure in which a semiconductor layer,a high-concentration layer and a conductive layer are stacked in thatorder; performing selective etching of the conductive layer and thehigh-concentration layer by using a resist reflow method, to form drainelectrodes and source electrodes for thin film transistors as well asdrain signal lines and to perform selective etching of the semiconductorlayer; forming pixel electrodes each of which is in part directlysuperposed on the source electrode of the corresponding one of the thinfilm transistors; and forming a protective film and opening, in theprotective film, apertures for exposing the respective pixel electrodes.

[0020] In the manufacturing method for the liquid crystal display deviceconstructed in this manner, although the formation of the semiconductorlayer and the formation of the drain electrode and the source electrodehave heretofore been performed with individual photo-processes, suchindividual photo-process can be replaced with one photo-process by usingthe resist reflow method, whereby it is possible to reduce the entiremanufacturing process.

[0021] At the same time that holes are formed in the protective film,holes at gate terminal parts and drain terminal parts are formed,whereby it is possible to reduce the entire manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention will become more readily appreciated and understoodfrom the following detailed description of preferred embodiments of theinvention when taken in conjunction with the accompanying drawings, inwhich:

[0023]FIG. 1 is a plan view showing one embodiment of a pixel of aliquid crystal display device according to the invention;

[0024]FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1;

[0025]FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 1;

[0026]FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 1;

[0027]FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 1;

[0028]FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. 1;

[0029]FIGS. 7A to 7C are process diagrams showing one embodiment of amanufacturing method for the gate signal lines GL shown in FIG. 1;

[0030]FIGS. 8A to 8F are process diagrams showing one embodiment of amanufacturing method for the thin film transistor shown in FIG. 1;

[0031]FIGS. 9A to 9H are process diagrams showing one embodiment of amanufacturing method for the liquid crystal display device shown in FIG.1;

[0032]FIG. 10 is a table showing one embodiment of a manufacturingmethod for the liquid crystal display device shown in FIG. 1;

[0033]FIG. 11 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a thin film transistor;

[0034]FIG. 12 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a drain signal line and the vicinity thereof;

[0035]FIG. 13 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a gate terminal part;

[0036]FIG. 14 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a drain terminal part;

[0037]FIGS. 15A to 15E are views showing another embodiment of theliquid crystal display device according to the invention, and areprocess diagrams showing one embodiment of a manufacturing method for athin film transistor;

[0038]FIGS. 16A to 16G are process diagrams showing one embodiment of amanufacturing method for the liquid crystal display device according tothe invention;

[0039]FIG. 17 is a table showing one embodiment of a manufacturingmethod for the liquid crystal display device according to the invention;

[0040]FIG. 18 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a thin film transistor;

[0041]FIG. 19 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a drain signal line and the vicinity thereof;

[0042]FIG. 20 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a gate terminal part;

[0043]FIG. 21 is a view showing another embodiment of the liquid crystaldisplay device according to the invention, and showing a cross sectionof a drain terminal part;

[0044]FIGS. 22A to 22G are views showing another embodiment of theliquid crystal display device according to the invention, and areprocess diagrams showing one embodiment of a manufacturing method for athin film transistor;

[0045]FIGS. 23A to 23G are process diagrams showing one embodiment of amanufacturing method for the liquid crystal display device according tothe invention;

[0046]FIG. 24 is a table showing one embodiment of a manufacturingmethod for the liquid crystal display device according to the invention;

[0047]FIG. 25 is a plan view showing one embodiment of a pixel of theliquid crystal display device according to the invention;

[0048]FIG. 26 is a cross-sectional view taken along line 26-26 of FIG.25;

[0049]FIG. 27 is a cross-sectional view taken along line 27-27 of FIG.25;

[0050]FIG. 28 is a plan view showing one embodiment of a pixel of theliquid crystal display device according to the invention;

[0051]FIG. 29 is a cross-sectional view taken along line 29-29 of FIG.28;

[0052]FIG. 30 is a cross-sectional view taken along line 30-30 of FIG.28;

[0053]FIG. 31 is a plan view showing one embodiment of a pixel of theliquid crystal display device according to the invention;

[0054]FIG. 32 is a cross-sectional view taken along line 32-32 of FIG.31;

[0055]FIG. 33 is a cross-sectional view taken along line 33-33 of FIG.31;

[0056]FIG. 34 is a cross-sectional view taken along line 34-34 of FIG.31;

[0057]FIG. 35 is a cross-sectional view showing one embodiment of a gateterminal part of the liquid crystal display device shown in FIG. 25;

[0058]FIG. 36 is a cross-sectional view showing one embodiment of adrain terminal part of the liquid crystal display device shown in FIG.25;

[0059]FIGS. 37A to 37F are process diagrams showing one embodiment of amanufacturing method for a thin film transistor of the liquid crystaldisplay device shown in FIG. 25;

[0060]FIGS. 38A to 38E are process diagrams showing one embodiment ofthe liquid crystal display device shown in FIG. 25;

[0061]FIG. 39 is a table showing one embodiment of the liquid crystaldisplay device shown in FIG. 25;

[0062]FIG. 40 is a plan view showing one embodiment of a pixel of theliquid crystal display device according to the invention;

[0063]FIG. 41 is a cross-sectional view taken along line 41-41 of FIG.40;

[0064]FIG. 42 is a cross-sectional view taken along line 42-42 of FIG.40;

[0065]FIG. 43 is an explanatory view showing a half-exposure method;

[0066]FIG. 44 is a cross-sectional view taken along line 44-44 of FIG.40;

[0067]FIG. 45 is a cross-sectional view taken along line 45-45 of FIG.40;

[0068]FIGS. 46A to 46D are process diagrams showing one embodiment of amanufacturing method for the thin film transistor shown in FIG. 40;

[0069]FIGS. 47E to 47H are process diagrams following FIG. 46D, showingone embodiment of a manufacturing method for the thin film transistorshown in FIG. 40;

[0070]FIG. 48I are a process diagram following FIG. 47H, showing oneembodiment of a manufacturing method for the thin film transistor shownin FIG. 40;

[0071]FIG. 49 is a plan view showing one embodiment of a pixel of theliquid crystal display device according to the invention;

[0072]FIG. 50 is a cross-sectional view taken along line 50-50 of FIG.49;

[0073]FIG. 51 is a cross-sectional view taken along line 51-51 of FIG.49;

[0074]FIG. 52 is a cross-sectional view showing the drain terminal partshown in FIG. 49;

[0075]FIGS. 53A to 53D are process diagrams showing one embodiment of amanufacturing method for the thin film transistor shown in FIG. 49; and

[0076]FIG. 54 is a view showing one embodiment of the equivalent circuitof the liquid crystal display device according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0077] Embodiments of the liquid crystal display device according to theinvention will be described below with reference to the accompanyingdrawings.

[0078] Embodiment 1.

[0079] <<Equivalent Circuit>>

[0080]FIG. 54 is an equivalent circuit diagram showing one embodiment ofthe liquid crystal display device according to the invention. FIG. 54 isa circuit diagram which is depicted to correspond to the actualgeometrical layout of the liquid crystal display device.

[0081] In FIG. 54, there is shown a transparent substrate SUB1. Thistransparent substrate SUB1 is disposed to be opposed to anothertransparent substrate SUB2 with a liquid crystal interposedtherebetween.

[0082] Gate signal lines GL and drain signal lines DL are formed on aliquid-crystal-side surface of the transparent substrate SUB1. The gatesignal lines GL are disposed to be extended in the x direction and to bejuxtaposed in the y direction as viewed in FIG. 54, while the drainsignal lines DL are insulated from the gate signal lines GL and aredisposed to be extended in the y direction and to be juxtaposed in the xdirection as viewed in FIG. 54. Rectangular areas each of which issurrounded by adjacent ones of the gate signal lines GL and adjacentones of the drain signal lines DL constitute pixel areas, respectively,and a display part AR is formed by an aggregation of these pixel areas.

[0083] A thin film transistor TFT and a pixel electrode PX are formed ineach of the pixel areas. The thin film transistor TFT is driven by thesupply of a scanning signal (voltage) from one of the adjacent gatesignal lines GL, and a video signal (voltage) is supplied to the pixelelectrode PX from one of the adjacent drain signal lines DL via the thinfilm transistor TFT.

[0084] A capacitance element Cadd is formed between the pixel electrodePX and the other of the adjacent gate signal lines GL so that when thethin film transistor is turned off, a video signal supplied to the pixelelectrode PX is stored in the capacitance element Cadd for a long time.

[0085] The pixel electrode PX in each of the pixel areas is arranged togenerate an electric field between the pixel electrode PX and a counterelectrode CT (not shown) formed in common to each of the pixel areas ona liquid-crystal-side surface of the other transparent substrate SUB2which is disposed to be opposed to the transparent substrate SUB1 withthe liquid crystal interposed therebetween. The optical transmissivityof the liquid crystal between each of the pixel electrodes PX and thecounter electrode CT is controlled by the electric field.

[0086] One end of each of the gate signal lines GL is formed to beextended to one side (in FIG. 54, the left-hand side) of the transparentsubstrate SUB1, and the extended portion (which will be hereinaftercalled a gate terminal part GTM) is connected to a bump of a verticalscanning circuit (semiconductor integrated circuit) V mounted on thetransparent substrate SUB1.

[0087] In addition, one end of each of the drain signal lines DL isformed to be extended to one side (in FIG. 54, the top side) of thetransparent substrate SUB1, and the extended portion (which will behereinafter called a drain terminal part DTM) is connected to a videosignal driver circuit (semiconductor integrated circuit) He mounted onthe transparent substrate SUB1.

[0088] The transparent substrate SUB2 is disposed to be opposed to thearea (display part AR) of the transparent substrate SUB1 that avoids anarea in which the vertical scanning circuit V and the video signaldriver circuit He are mounted.

[0089] The transparent substrate SUB2 is secured to the transparentsubstrate SUB1 by a sealing material SL formed in the periphery of thetransparent substrate SUB2, and this sealing material SL also has thefunction of sealing the liquid crystal between the transparentsubstrates SUB1 and SUB2.

[0090] <<Construction of Pixel>>

[0091]FIG. 1 shows the construction of one pixel (corresponding to theportion shown in a dotted frame A of FIG. 54) on the liquid-crystal-sidesurface of the transparent substrate SUB1, as well as the constructionsof terminal parts for supplying a scanning signal and a video signal tothe pixel. FIG. 2 shows a cross-sectional view taken along line 2-2 ofFIG. 1, FIG. 3 shows a cross-sectional view taken along line 3-3 of FIG.1, FIG. 4 shows a cross-sectional view taken along line 4-4 of FIG. 1,FIG. 5 shows a cross-sectional view taken along line 5-5 of FIG. 1, andFIG. 6 shows a cross-sectional view taken along line 6-6 of FIG. 1.

[0092] The gate signal lines GL disposed to be extended in the xdirection and to be juxtaposed in the y direction as viewed in FIG. 1are formed on the liquid-crystal-side surface of the transparentsubstrate SUB1. Each of these gate signal lines GL is made of atwo-layer structure which includes an ITO (Indium-tin-Oxide) film as itslower layer and a molybdenum (MO) film as its upper layer.

[0093] One end (in FIG. 1, the left-hand side) of each of the gatesignal lines GL is formed to be extended outwardly from the display partAR, and the extended portion is formed as the gate terminal part GTMhaving a comparatively large area.

[0094] The gate signal lines GL and the drain signal lines DL which willbe described later surround the rectangular area, and this rectangulararea is constructed as a pixel area.

[0095] A portion of each of the gate signal lines GL has an extendedportion which projects into the pixel area, and this extended portionhas the function of the gate electrode of the thin film transistor TFTwhich will be described later.

[0096] In addition, another portion of each of the gate signal lines GLhas an extended portion which projects into another pixel area disposedadjacently to the pixel area in the −y direction, and this extendedportion has the function of one electrode of the capacitance elementCadd (the other electrode of which is the pixel electrode PX).

[0097] In the pixel area, light shield films SKD are formed to runadjacently to and in parallel with the respective drain signal lines DL.These light shield films SKD are formed in parallel with the gate signallines GL, and have a two-layer structure which includes an ITO film asits lower layer and a Mo film as its upper layer.

[0098] These light shield films SKD, together with a black matrix BMformed on the glass substrate SUB2, can highly reliably block light dueto the disorder of alignment of the liquid crystal in the periphery ofthe pixel electrode PX (particularly, along the sides of the pixelelectrode PX that are parallel to the y direction in FIG. 1).

[0099] An insulating film GI (refer to FIGS. 2 and 6) is formed on theliquid-crystal-side surface of the transparent substrate SUB1 on whichthe gate signal lines GL and the light shield films SKD are formed inthe above-described manner. This insulating film GI has the function ofan interlayer insulating film between the gate signal lines GL and thedrain signal lines DL which will be described later, the function ofgate insulating films for the thin film transistors TFT which will bedescribed later, and the function of dielectric films for thecapacitance elements Cadd which will be described later.

[0100] A semiconductor layer AS made of, for example, amorphous Si(a-Si) is formed on the upper surface of the insulating film GI in sucha manner as to traverse the extended portion of each of the gate signallines GL that projects into the pixel area.

[0101] This semiconductor layer AS constitutes the semiconductor layerof the thin film transistor TFT, and a drain electrode SD1 and a sourceelectrode SD2 are formed on the upper surface of the semiconductor layerAS, whereby a reversed staggered structure MIS transistor is formedwhich uses the extended portion of the gate signal line GL as its gateelectrode.

[0102] Incidentally, this semiconductor layer AS is formed not only inthe region in which the thin film transistor TFT is formed, but isformed to be integrally extended into the region in which the drainsignal line DL to be described later is formed. This construction isintended to strengthen the interlayer insulation of the drain signalline DL from the gate signal line GL.

[0103] The drain electrode SD1 and the source electrode SD2 on thesemiconductor layer AS are formed at the same time as the drain signalline DL.

[0104] Specifically, the drain signal lines DL which are disposed to beextended in the y direction and to be juxtaposed in the x direction asviewed in FIG. 1 are formed on the upper surface of the insulating filmGI (the semiconductor layer AS underlies the drain signal lines DL), anda part of each of the drain signal lines DL is formed to be extended tothe upper surface of the semiconductor layer AS of the thin filmtransistor TFT and forms the drain electrode SD1.

[0105] Incidentally, one end (in FIG. 1, the top side) of each of thedrain signal lines DL is formed to be extended outwardly from thedisplay part AR, and the extended portion is formed as the gate terminalpart GTM having a comparatively large area.

[0106] The source electrode SD2 is formed to be spaced apart from thedrain electrode SD1 by a distance equivalent to the channel length ofthe thin film transistor TFT.

[0107] This source electrode SD2 is formed to be extended into the pixelarea from above the semiconductor layer AS of the thin film transistorTFT, and this extended portion is formed as a part for connection to thepixel electrode PX which will be described later.

[0108] The drain signal lines DL, the drain electrodes SD1 and thesource electrodes SD2 are formed of, for example, molybdenum (Mo).

[0109] Incidentally, a high-concentration layer d₀ doped with animpurity is formed at the interface between the semiconductor layer ASand each of the source electrode SD2 and the drain electrode SD1 (referto FIG. 2). This high-concentration layer d₀ functions as a contactlayer of the thin film transistor TFT.

[0110] In addition, the high-concentration layer d₀ is formed at theinterface between the drain signal lines DL and the underlyingsemiconductor layer AS (refer to FIG. 4).

[0111] The pixel electrode PX made of, for example, ITO(Indium-Tin-Oxide) film is formed on the central portion of the uppersurface of the insulating film GI except the narrow periphery thereofwithin the pixel area.

[0112] The side of the pixel electrode PX that is adjacent to the thinfilm transistor TFT is formed to avoid the region in which the thin filmtransistor TFT is formed and to be superposed on and connected to theextended portion of the source electrode SD2.

[0113] The sides of the pixel electrode PX that are adjacent to therespective drain signal lines DL are formed so that the outlines of therespective sides are superposed on the central axes (or approximatelycentral axes) of the respective light shield films SKD.

[0114] Each of the light shield films SKD mainly functions to blocklight leak due to an electric field generated between the pixelelectrode PX and an adjacent one of the drain signal lines DL as well aslight due to the alignment disorder of the liquid crystal due to anelectric field generated from the adjacent one of the drain signal linesDL in the periphery of the pixel electrode PX.

[0115] Furthermore, the pixel electrode PX is formed to slightly overlapthe gate signal line GL for driving the thin film transistor TFT and theother gate signal line GL (the gate signal line GL shown on the upperside of FIG. 1) which is disposed adjacent to the gate signal line GLwith the pixel electrode PX interposed therebetween.

[0116] The other gate signal line GL has an extended portion whichprojects into the pixel area as described previously, and the pixelelectrode PX is superposed on the other gate signal line GL via theinsulating film GI in a comparatively large area.

[0117] The capacitance element Cadd which uses the insulating film GI asits dielectric film is formed in the portion in which the pixelelectrode PX and the other gate signal line GL are superposed on eachother. The capacitance element Cadd serves, for example, the effect ofenabling a video signal supplied to the pixel electrode PX to be storedfor a comparatively long time even when the thin film transistor TFT isturned off.

[0118] A protective film PSV which is made of, for example, SiN isformed on the surface of the transparent substrate SUB1 formed in theabove-described manner.

[0119] This protective film PSV is provided for preventing the thin filmtransistor TFT from coming into direct contact with the liquid crystal,and apertures are formed in the areas of the protective film PSV inwhich the respective pixel electrodes PX are formed.

[0120] Specifically, the protective film PSV is formed so that thecentral portion of the pixel electrode PX except the periphery thereofis exposed (refer to FIG. 2). In this construction, since the protectivefilm PSV is absent in the portion of the pixel area through which totransmit light, it is possible to prevent the absorption of light intothe protective film PSV.

[0121] An alignment layer ORI which covers the entire area of thedisplay part AR is formed on the surface of the transparent substrateSUB1 formed in the above-described manner (refer to FIG. 4), and servesto determine the initial alignment direction of a liquid crystal LCwhich is in direct contact with the alignment layer ORI.

[0122] As shown in FIG. 4, the black matrix BM is formed on theliquid-crystal-LC-side surface of the transparent substrate SUB2 so asto partition each of the pixel areas from the adjacent one. Colorfilters FIL having colors corresponding to the respective pixel areasare individually formed in apertures formed in the portions of the blackmatrix BM that correspond to the respective pixel areas.

[0123] Another alignment layer ORI which covers the entire area of thedisplay part AR is formed on the surface of the transparent substrateSUB2 formed in the above-described manner, and serves to determine theinitial alignment direction of the liquid crystal LC which is in directcontact with the alignment layer ORI.

[0124] <<GATE SIGNAL LINE GL>>

[0125] Each of the gate signal lines GL is made of a two-layerstructure, and its lower layer is made of an ITO (Indium-Tin-Oxide) filmg1, while its upper layer is made of a Mo layer g2, as shown in FIG. 2or 3 by way of example.

[0126] In the recent trend toward increased sizes of liquid crystaldisplay panels, it has been desired to reduce the resistivity of each ofthe gate signal lines GL, and the Mo layer g2 is selected as the mainmaterial of the gate signal lines GL. However, if the Mo layer g2 isused as a single layer, the adhesion of the Mo layer g2 to thetransparent substrate SUB1 which is a base substrate becomesinsufficient. For this reason, the ITO film g1 is used as anintermediate layer.

[0127] By subjecting each of the gate signal lines GL having thetwo-layer structure to selective etching which allows for the etchingrates of the respective layers (as will be described later), taperedsurfaces which become gradually more open toward the transparentsubstrate SUB1 can be formed on the side walls of each of the gatesignal lines GL, whereby it is possible to prevent so-called climb-overdisconnection of the drain signal lines DL which climb over the gatesignal lines GL and it is also possible to prevent so-called climb-overdamage to the protective film PSV.

[0128] During the formation of the gate terminal parts GTM of therespective gate signal lines GL, there may be a case where selectivityto the Mo layer g2 cannot be ensured when contact holes are to be formedby dry-etching the protective film PSV and the insulating film GI.However, since the ITO film g1 remains as a so-called stopper, the gateterminal parts GTM can be formed with good reliability.

[0129]FIGS. 7A to 7C are process diagrams showing one embodiment of amethod of forming one of the above-described gate signal lines GL.

[0130] First, as shown in FIG. 7A, the ITO film g1 is formed on the mainsurface of the transparent substrate SUBI, and the Mo layer g2 is formedon the upper surface of the ITO film g1. Then, a photoresist film PRESis formed on the surface of the Mo layer g2, and this photoresist filmPRES is selectively exposed by using a photomask (not shown). Afterthat, the photoresist film PRES is developed so that the photoresistfilm PRES is left in an area in which to form the gate signal line GL.

[0131] Then, the photoresist film PRES is used as a mask to selectivelyetch the portion of the Mo layer g2 that is exposed from this mask. Theetching solution used in this step is selected from, for example, amixed acid containing phosphoric acid and nitric acid and a mixedsolution of cerium nitrate and nitric acid. In this case, taperedsurfaces which become gradually more open toward the transparentsubstrate SUB1 are respectively formed on the side walls of theremaining Mo layer g2.

[0132] Then, the photoresist film PRES is again used as a mask toselectively etch the portion of the ITO film g1 that is exposed fromthis mask. The etching solution used in this step is, for example, aquaregia (a mixed solution of hydrochloric acid and nitric acid). In thiscase, tapered surfaces which become gradually more open toward thetransparent substrate SUB1 are respectively formed on the side walls ofthe remaining Mo layer g1.

[0133] After that, the photoresist film PRES is removed, whereby thegate signal line GL is formed on the transparent substrate SUB1. Thisgate signal line GL has side walls which respectively have gentlytapered surfaces which become gradually more open toward the transparentsubstrate SUB1, whereby it is possible to fully prevent a layer to bestacked in a later step from undergoing damages such as cuttings due tosteps.

[0134] <<DRAIN SIGNAL LINE DL>>

[0135] A cross section of one of the drain signal lines DL is clearlyshown in FIG. 4. The shown drain signal line DL is formed in parallelwith the thin film transistors TFT formed by a resist reflow methodwhich will be described later, and is made of a stacked structure inwhich the semiconductor layer AS made of a-Si, the high-concentrationlayer d₀ formed on the surface of the semiconductor layer AS, and a Molayer d₁ are stacked in that order.

[0136] Accordingly, as shown in FIG. 4, tapered surfaces which becomegradually more open toward the transparent substrate SUB1 arerespectively formed on the side walls of the drain signal line DL, andsteps are respectively formed midway on these tapered surfaces,specifically, in the portion of the semiconductor layer AS thatunderlies the high-concentration layer d₀.

[0137] Therefore, it is possible to reliably prevent the drain signalline DL from causing so-called climb-over damage to the protective filmPSV and the alignment layer ORI.

[0138] The climb-over damage occurring in this case causes the problemthat a crack or the like occurs in the protective film PSV in thevicinity of either of the side walls of the drain signal line DL and thematerial of the drain signal line DL is ionized through this crack andsolved out in the liquid crystal, thus changing the resistivity of theliquid crystal.

[0139] <<THIN FILM TRANSISTOR TFT>>

[0140]FIG. 2 is a view showing a cross section of one of the thin filmtransistors TFT. The shown thin film transistor TFT is formed by using aso-called resist reflow method which will be described later.

[0141] The gate signal line GL which constitutes part of the gateelectrode of the thin film transistor TFT has side walls formed in atapered shape which becomes gradually more open toward the transparentsubstrate SUB1, whereby the insulating film GI, the drain electrode SD1and the source electrode SD2 are stacked in that portion can beprevented from being damaged by steps.

[0142] The pixel electrode PX electrically connected to the sourceelectrode SD2 of the thin film transistor TFT is formed to be directlystacked on the source electrode SD2. Accordingly, the protective filmPSV which prevents the thin film transistor TFT from coming in directcontact with the liquid crystal LC is formed to overlie the pixelelectrode PX.

[0143] Specifically, the pixel electrode PX is positioned as a layerwhich underlies the protective film PSV, whereby the formation of acontact hole to the protective film PSV is avoided with respect to theelectrical connection between the source electrode SD2 of the thin filmtransistor TFT and the pixel electrode PX.

[0144] The thin film transistor TFT formed by a resist reflow method hasside walls formed by a stacked structure in which the semiconductorlayer AS, the high-concentration layer d₀ and the drain electrode SD1 orthe source electrode SD2 are stacked in that order. The respective sidewalls are formed to have tapered surfaces which become gradually moreopen toward the transparent substrate SUB1, and steps are respectivelyformed midway on these tapered surfaces, specifically, in the portion ofthe semiconductor layer AS that underlies the high-concentration layerd₀.

[0145] Therefore, it is possible to reliably prevent the drain signalline DL from causing so-called climb-over damage to the protective filmPSV and the alignment layer ORI.

[0146] In particular, the pixel electrode PX is made of a material whichis comparatively easily damaged at a location where the pixel electrodePX climbs over a step. In addition, the pixel electrode PX must beformed to climb over the stacked structure and overlap the sourceelectrode SD2. However, since the steps are respectively formed on thetapered surfaces of the side walls of the stacked structure, the pixelelectrode PX can be fully prevented from undergoing climb-over damagedue to the step.

[0147]FIGS. 8A to 8F are process diagrams showing one embodiment of amethod of forming the above-described thin film transistor TFT.

[0148] First, as shown in FIG. 8A, after a gate signal line GL and aninsulating film GI have been formed, a semiconductor layer AS is formedon the surface of this insulating film GI and a high-concentration layerd₀ is formed on the surface of the semiconductor layer AS, and a Molayer d₁ is formed on the high-concentration layer d₀. In this case, thesemiconductor layer AS, the high-concentration layer d₀ and the Mo layerd₁ are continuously deposited in the same chamber.

[0149] As shown in FIG. 8B, a photoresist film PRES is formed on thesurface of the Mo layer d₁, and the portions of the photoresist filmPRES that correspond to portions in which to form a drain signal lineDL, a drain electrode SD1 and a source electrode SD2 are left throughselective exposure using a photomask.

[0150] As shown in FIG. 8C, the photoresist film PRES is used a mask,and the portion of the Mo layer d₁ that is exposed from this mask isselectively etched (for example, a mixed acid containing phosphoric acidand nitric acid or a mixed solution of cerium nitrate and nitric acid isselected for this etching), and further, the high-concentration layer d₀is dry-etched. In this case, the surface of the semiconductor layer ASis cut to a slight extent.

[0151] Incidentally, the etching of the high-concentration layer d₀ isnot limited to only the above-described method, and after the selectiveetching of the Mo layer d₁, this Mo layer d₁ may be used as a mask toetch the high-concentration layer d₀.

[0152] As shown in FIG. 8D, the photoresist film PRES is made to reflow.By this treatment, the peripheral portions of the photoresist film PRESare sagged, and the sagged portions also function as a mask. The methodof reflowing the photoresist film PRES is, for example, baking,dissolution in an organic solvent atmosphere or immersion in water.

[0153] In this step, the sags of the photoresist film PRES need tocompletely cover the portion (channel region) between the drainelectrode SD1 and the source electrode SD2. To this end, in the stepshown in FIG. 8B, the pattern width of the photoresist film PRES in thisportion needs to be made as narrow as possible.

[0154] Furthermore, this photoresist film PRES is used as a mask toselectively etch the portion of the semiconductor layer AS that isexposed from this mask.

[0155] Then, the photoresist film PRES is removed. It is preferable tosubject the photoresist film PRES to so-called MEA stripping afterashing has been performed, because if the baking of the photoresist filmPRES is performed during the reflow thereof, the photoresist film PRESbecomes difficult to strip.

[0156] As shown in FIG. 8E, an ITO film ITO1 is formed, and aphotoresist film PRES is formed in a portion which corresponds to anarea in which to form a pixel electrode PX (as well as a drain terminalpart DTM). This photoresist film PRES is used as a mask to remove theportion of the ITO film ITO1 that is exposed from this mask. After that,the photoresist film PRES is removed.

[0157] As shown in FIG. 8F, a protective film PSV is formed, and aphotoresist film PRES is formed so that an aperture is formed in thecentral portion of the pixel area (including the region in which thethin film transistor TFT is formed) except the periphery of the pixelarea.

[0158] This photoresist film PRES is used as a mask to remove theportion of the protective film PSV that is exposed from this mask.Incidentally, at the same time that holes are formed in this protectivefilm PSV, holes at the gate terminal parts GTM and the drain terminalparts DTM are also formed. After that, the photoresist film PRES isremoved.

[0159] <<CAPACITANCE ELEMENT Cadd>>

[0160]FIG. 3 is a view showing a cross section of one of the capacitanceelements Cadd. The pixel electrode PX is formed in such a manner that apart of the pixel electrode PX is superposed on a part of the gatesignal line GL with the insulating film GI interposed therebetween, andthe insulating film GI serves as the dielectric film of the capacitanceelement Cadd.

[0161] As described above, since the pixel electrode PX is formed to bepositioned as a layer underlying the protective film PSV, the dielectricfilm of the capacitance element Cadd does not use a two-layer structuremade of the protective film PSV and the insulating film GI, and isformed of only the insulating film GI.

[0162] For this reason, the capacitance value of the capacitance elementCadd can be set by the film thickness of the insulating film GI and thearea of superposition between the gate signal line GL and the pixelelectrode PX, whereby the capacitance value of the capacitance elementCadd can readily be set.

[0163] Steps due to the gate signal line GL easily appear on the surfaceof the dielectric film of the capacitance element Cadd owing to the factthat the dielectric film is formed of only the insulating film GI.However, the gate signal line GL has a two-layer structure whichincludes the ITO film g1 as its lower layer and the Mo layer g2 as itsupper layer, and the side walls of the gate signal line GL is formed inthe shape of a gentle taper, whereby in the case where part of the pixelelectrode PX is superposed on the gate signal line GL, it is possible tofully prevent the pixel electrode PX from being damaged at a locationwhere the pixel electrode PX climbs over a step.

[0164] <<BLACK MATRIX BM>>

[0165] A cross section of the black matrix BM is shown in FIG. 4. FIG. 4shows that the black matrix BM is formed to cover only the drain signalline DL, but the black matrix BM is also formed to cover the gate signallines GL and the thin film transistors TFT.

[0166] This construction is intended to improve contrast and to preventa variation in the characteristics of the thin film transistor TFT dueto irradiation with external light.

[0167] The light shield films SKD which are formed at the same time asthe gate signal lines GL are formed on the opposite sides of the drainsignal line DL, and the black matrix BM which covers the drain signalline DL is formed so that the widthwise opposite ends of the blackmatrix BM are respectively positioned over the light shield films SKD.

[0168] <<GATE TERMINAL PART GTM>>

[0169]FIG. 5 is a view showing a cross section of one of the gateterminal parts GTM. The shown gate terminal part GTM is formed byopening apertures, respectively, in the protective film PSV and theinsulating film GI in that order (by selective etching using dryetching) and exposing an extending end of the gate signal line GL. Theopening of the apertures is performed at the same time as the opening ofapertures in the protective film PSV in the respective pixel areas.

[0170] As is apparent from FIG. 5, the gate signal line GL which hasbeen formed of the ITO film g1 as the lower layer and the Mo layer g2 asthe upper layer is formed with the overlying Mo layer g2 being removedat the gate terminal part GTM. This is because the Mo layer g2 for whichno selection ratio can be ensured is etched while the apertures arebeing opened in the protective film PSV and the insulating film GI bydry etching.

[0171] However, the underlying ITO film g1 having the function of astopper of the etching is left, and the function of the gate terminalpart GTM is fully realized by the ITO film g1. In addition, the ITO filmg1 is made of a material which cannot easily be oxidized, whereby it ispossible to form, for example, the gate terminal part GTM havingreliability in resistance to electrolytic corrosion.

[0172] <<DRAIN TERMINAL PART DTM>>

[0173]FIG. 6 is a view showing a cross section of one of the drainterminal parts DTM. The shown drain terminal part DTM is formed byopening an aperture in the protective film PSV (by selective etching)and exposing an extending end of the drain signal line DL. The openingof the aperture is performed at the same time as the opening ofapertures in the protective film PSV in the respective pixel areas.

[0174] In this construction, the ITO film ITO1 is formed to cover thedrain signal line DL at the drain terminal part DTM. This ITO film ITO1is formed at the same time that the pixel electrode PX is formed. TheITO film ITO1 is formed so that the occurrence of electrolytic corrosioncan be prevented.

[0175] As described above, the drain signal line DL is formed inparallel with the thin film transistors TFT formed by the resist reflowmethod, and is made of a stacked structure in which the semiconductorlayer AS, the high-concentration layer d₀ and the Mo layer d₁ arestacked in that order. The side walls of the drain signal line DL isformed in the shape of a gentle taper.

[0176] Accordingly, in the case where the drain signal line DL iscovered with the ITO film ITO1 at the drain terminal part DTM, it ispossible to solve a problem such as the cuttings of the ITO film ITO1due to steps.

[0177] <<MANUFACTURING METHOD>>

[0178]FIGS. 9A to 9H are process diagrams showing one embodiment of amanufacturing method for the above-described liquid crystal displaydevice.

[0179]FIGS. 9A to 9H are views showing the process diagrams for formingthe portion of the gate terminal part GTM, together with the processdiagrams shown in FIGS. 8A to 8F.

[0180]FIG. 9A corresponds to FIG. 8A, FIG. 9B corresponds to FIG. 8B,FIG. 9C corresponds to FIG. 8C, FIG. 9D corresponds to FIG. 8D, FIG. 9Ecorresponds to FIG. 8E, and FIG. 9G corresponds to FIG. 8F.

[0181] A series of processes is as shown in the Table of FIG. 10. As isapparent from this table, the number of photo-processes can be reducedto four, specifically, the patterning of the gate signal lines GL, thepatterning of the drain signal lines DL (the drain electrodes and thesource electrodes), the patterning of the pixel electrodes PX and thepattering of the protective film PSV.

[0182] Embodiment 2.

[0183] In the above description of Embodiment 1, reference has been madeto the liquid crystal display device in which the thin film transistorsTFT are formed by using the resist reflow method. However, the inventioncan also be applied to a liquid crystal display device in which its thinfilm transistors TFT are formed by using a so-called half-exposuremethod.

[0184] Embodiment 2 is the same as Embodiment 1 except the followingconstruction.

[0185] <<THIN FILM TRANSISTOR TFT>>

[0186]FIG. 11 is a view showing a cross section of a thin filmtransistor TFT formed by using a so-called half-exposure method.

[0187] The thin film transistor TFT has side walls formed by a stackedstructure in which a semiconductor layer AS, a high-concentration layerd₀ and a Mo layer d₁ are stacked in that order, and the respective sidewalls are formed to have gently tapered surfaces which become graduallymore open toward the transparent substrate SUB1.

[0188]FIGS. 15A to 15E are process diagrams showing one embodiment of amethod of forming the thin film transistor TFT.

[0189] First, as shown in FIG. 15A, after a gate signal line GL and aninsulating film GI have been formed, the semiconductor layer AS isformed on the surface of this insulating film GI and thehigh-concentration layer d₀ is formed on the surface of thesemiconductor layer AS, and the Mo layer d₁ is formed on thehigh-concentration layer d₀. In this case, the semiconductor layer AS,the high-concentration layer d₀ and the Mo layer d₁ are continuouslydeposited in the same chamber.

[0190] As shown in FIG. 15B, a photoresist film PRES is formed on thesurface of the Mo layer d₁, and selective exposure using a photomask isperformed. The photomask used in this case is either a mask having agrid structure or a mask fabricated by controlling the film thickness ofa semi-transparent film such as MoSi, and the photoresist film PRES isleft by using the photomask in portions which correspond to portions inwhich to form a drain signal line DL, a drain electrode SD1 and a sourceelectrode SD2 and in a portion which corresponds to the portion (channelportion) between the drain electrode SD1 and the source electrode SD2.In this case, the film thickness of the photoresist film PRES over thechannel portion is made smaller than the film thickness of thephotoresist film PRES over the other regions.

[0191] Specifically, in the channel portion, resist conditions arecontrolled so that the time of completion of etching of the photoresist,the Mo layer d₁ and the high-concentration layer d₀ becomes(approximately) the same as the time of completion of etching of the Molayer d₁, the high-concentration layer d₀ and the semiconductor layerAS.

[0192] As shown in FIG. 15C, the photoresist film PRES is used a mask,and the portion of the Mo layer d₁ that is exposed from this mask isselectively etched (for example, a mixed acid containing phosphoric acidand nitric acid or a mixed solution of cerium nitrate and nitric acid isselected for this etching), and further, the high-concentration layer d₀and the semiconductor layer AS are dry-etched. In this case, in thechannel portion, the Mo layer d₁ and the high-concentration layer d₀ aswell as the semiconductor layer AS are etched, but the surface of thesemiconductor layer AS is only cut to a slight extent.

[0193] Incidentally, the etching of the high-concentration layer d₀ isnot limited to only the above-described method, and after the selectiveetching of the Mo layer d₁, this Mo layer d₁ may be used as a mask toetch the high-concentration layer d₀.

[0194] After that, the photoresist film PRES is removed.

[0195] As shown in FIG. 15D, an ITO film ITO1 is formed, and aphotoresist film PRES is formed in a portion which corresponds to anarea in which to form a pixel electrode PX (as well as a drain terminalpart DTM). This photoresist film PRES is used as a mask to remove theportion of the ITO film ITO1 that is exposed from this mask. After that,the photoresist film PRES is removed.

[0196] As shown in FIG. 15E, a protective film PSV is formed, and aphotoresist film PRES is formed so that an aperture is formed in thecentral portion of the pixel area (including the region in which thethin film transistor TFT is formed) except the periphery of the pixelarea.

[0197] This photoresist film PRES is used as a mask to remove theportion of the protective film PSV that is exposed from this mask.Incidentally, at the same time that holes are formed in this protectivefilm PSV, holes at the gate terminal parts GTM and the drain terminalparts DTM are also formed. After that, the photoresist film PRES isremoved.

[0198] <<DRAIN SIGNAL LINE DL>>

[0199] A cross section of one of drain signal lines DL is shown in FIG.12. The shown drain signal line DL is made of a stacked structure inwhich the semiconductor layer AS, the high-concentration layer d₀ andthe Mo layer d₁ are stacked in that order, and is formed in parallelwith the thin film transistors TFT formed by the half-exposure method.Accordingly, as shown in FIG. 12, tapered surfaces which becomegradually more open toward the transparent substrate SUB1 arerespectively formed on the side walls of the drain signal line DL.

[0200] <<GATE TERMINAL PART GTM>>

[0201] A cross section of one of the gate terminal parts GTM is shown inFIG. 13. The shown gate signal line GTM is formed similarly to the caseof Embodiment 1.

[0202] <<DRAIN TERMINAL PART DTM>>

[0203] A cross section of one of the drain terminal parts DTM is shownin FIG. 14. The shown drain terminal part DTM is made of a stackedstructure in which the semiconductor layer AS, the high-concentrationlayer d₀ and the Mo layer d₁ are stacked in that order, and taperedsurfaces which become gradually more open toward the transparentsubstrate SUB1 are respectively formed on the side walls of the drainsignal line DL.

[0204] At the drain terminal part DTM, the ITO film ITO1 is formed toextend to the side walls of the drain signal line DL. The ITO film ITO1is formed at the same time that the pixel electrode PX is formed forpreventing the electric corrosion.

[0205] The drain terminal part DTM is formed by opening an aperture inthe protective film PSV and exposing the ITO film ITO1.

[0206] <<MANUFACTURING METHOD>>

[0207]FIGS. 16A to 16G are process diagrams showing one embodiment of amanufacturing method for the above-described liquid crystal displaydevice.

[0208]FIGS. 16A to 16G are views showing the process diagrams forforming the portion of the gate terminal part GTM, together with theprocess diagrams shown in FIGS. 15A to 15E.

[0209]FIG. 16A corresponds to FIG. 15B, FIG. 16C corresponds to FIG.15C, FIG. 16D corresponds to FIG. 15D, and FIG. 9F corresponds to FIG.15E.

[0210] A series of processes is as shown in the Table of FIG. 17. As isapparent from this table, the number of photo-processes can be reducedto four, specifically, the patterning of the gate signal lines GL, thepatterning of the drain signal lines DL (the drain electrodes and thesource electrodes), the patterning of the pixel electrodes PX and thepattering of the protective film PSV.

[0211] Embodiment 3.

[0212] The invention can also be applied to a liquid crystal displaydevice in which its thin film transistors TFT are formed by using aso-called ITO mask method.

[0213] Embodiment 3 is the same as Embodiment 1 except the followingconstruction.

[0214] <<THIN FILM TRANSISTOR TFT>>

[0215]FIG. 18 is a view showing a cross section of a thin filmtransistor TFT formed by using an ITO mask method.

[0216] In the thin film transistor TFT, the ITO film ITO1 of the pixelelectrode PX is directly superposed on not only the entire surface ofthe source electrode SD2, but also the surface of the drain signal lineDL (and the drain electrode SD1).

[0217] Similarly to the case of the other embodiments, the side walls ofa stacked structure in which the semiconductor layer AS, thehigh-concentration layer d₀ and the Mo layer d₁ are stacked in thatorder are respectively formed to have gently tapered surfaces whichbecome gradually more open toward the transparent substrate SUB1.

[0218]FIGS. 22A to 22G are process diagrams showing one embodiment of amethod of forming the thin film transistor TFT.

[0219] First, as shown in FIG. 22A, after a gate signal line GL and aninsulating film GI have been formed, the semiconductor layer AS isformed on the surface of this insulating film GI and thehigh-concentration layer d₀ is formed on the surface of thesemiconductor layer AS, and the Mo layer d₁ is formed on thehigh-concentration layer d₀. In this case, the semiconductor layer AS,the high-concentration layer d₀ and the Mo layer d₁ are continuouslydeposited in the same chamber.

[0220] As shown in FIG. 22B, a photoresist film PRES is formed on thesurface of the Mo layer d₁, and through selective exposure using aphotomask, the photoresist film PRES is left in portions whichcorrespond to portions in which to form a drain signal line DL, a drainelectrode SD1 and a source electrode SD2 and in a portion whichcorresponds to the region (channel portion) between the drain electrodeSD1 and the source electrode SD2.

[0221] Then, the photoresist film PRES is used a mask, and the portionof the Mo layer d₁ that is exposed from this mask, thehigh-concentration layer d₀ and the semiconductor layer AS areselectively etched in that order. After that, the photoresist film PRESis removed.

[0222] As shown in FIG. 22C, an ITO film ITO is formed, and aphotoresist film PRES is formed on the upper surface of the ITO filmITO. The photoresist film PRES is left in a portion which corresponds toan area in which to form the drain signal line DL, the drain electrodeSD1 and the pixel electrode PX.

[0223] As shown in FIG. 22D, the photoresist film PRES is used as a maskto selectively etch the portion of the ITO film ITO that is exposed fromthis mask. After that, the photoresist film PRES is removed.

[0224] As shown in FIG. 22E, the ITO film ITO is used as a mask toselectively etch the portion of the Mo layer d₁ that is exposed fromthis mask, and furthermore, the high-concentration layer d₀ isselectively etched. Thus, the surface of the semiconductor layer AS isexposed.

[0225] As shown in FIG. 22F, a protective film PSV is formed, and aphotoresist film PRES is formed so that an aperture is formed in thecentral portion of the pixel area (including the region in which thethin film transistor TFT is formed) except the periphery of the pixelarea.

[0226] This photoresist film PRES is used as a mask to remove theportion of the protective film PSV that is exposed from this mask.Incidentally, at the same time that holes are formed in this protectivefilm PSV, holes at the gate terminal parts GTM and the drain terminalparts DTM are also formed. After that, the photoresist film PRES isremoved, as shown in FIG. 22G.

[0227] <<DRAIN SIGNAL LINE DL>>

[0228] A cross section of one of drain signal lines DL is shown in FIG.19. The shown drain signal line DL is made of a stacked structure inwhich the semiconductor layer AS, the high-concentration layer d₀, theMo layer d₁ and the ITO film ITO1 are stacked in that order.

[0229] <<GATE TERMINAL PART GTM>>

[0230] A cross section of one of the gate terminal parts GTM is shown inFIG. 20. The shown gate terminal part GTM has a construction similar tothat of the gate terminal part GTM of each of Embodiments 1 and 2.

[0231] <<DRAIN TERMINAL PART DTM>>

[0232] A cross section of one of the drain terminal parts DTM is shownin FIG. 21. At the drain terminal part DTM, since the drain signal lineDL is made of the above-described stacked structure, the ITO film ITO1is exposed at the bottom of the aperture of the protective film PSV sothat it is possible to obtain a construction having reliability inresistance to electrolytic corrosion.

[0233] <<MANUFACTURING METHOD>>

[0234]FIGS. 23A to 23G are process diagrams showing one embodiment of amanufacturing method for the above-described liquid crystal displaydevice.

[0235]FIGS. 23A to 23G are views showing the process diagrams forforming the portion of the gate terminal part GTM, together with theprocess diagrams shown in FIGS. 22A to 22G.

[0236]FIG. 23A corresponds to FIG. 22B, FIG. 23C corresponds to FIG.22C, FIG. 23D corresponds to FIG. 22D, FIG. 23E corresponds to FIG. 22E,FIG. 23F corresponds to FIG. 22F, and FIG. 23G corresponds to FIG. 22G.

[0237] A series of processes is as shown in the Table of FIG. 24. As isapparent from this table, the number of photo-processes can be reducedto four, specifically, the patterning of the gate signal lines GL, thepatterning of the pixel electrodes PX (the drain signal lines DL), thepatterning of the drain electrodes and the source electrodes, and thepattering of the protective film PSV.

[0238] Embodiment 4.

[0239] In the above description of each of the embodiments, referencehas been made to a so-called vertical electric field type of liquidcrystal display device in which a pixel electrode is formed in eachpixel area on its transparent substrate SUB1 and a counter electrodecommon to each pixel area is formed on its glass substrate SUB2 so thatthe optical transmissivity of its liquid crystal is controlled by anelectric field generated between each of these electrodes approximatelyperpendicularly to the substrates.

[0240] However, the invention is not limited to such a vertical electricfield type of liquid crystal display device, and can also be applied toa so-called in-plane-switching type of liquid crystal display device inwhich a pixel electrode and a counter electrode are formed in each pixelarea on its transparent substrate SUB1 so that the opticaltransmissivity of its liquid crystal is controlled by an electric fieldcomponent generated between the pixel electrode and the counterelectrode approximately in parallel with the transparent substrate SUB1.

[0241]FIG. 25 is a plan view showing the construction of a pixel on thein-plane-switching type of liquid crystal display device, andcorresponds to FIG. 1. Incidentally, FIG. 26 shows a cross-sectionalview taken along line 26-26 of FIG. 25 and FIG. 27 shows across-sectional view taken along line 27-27 of FIG. 25.

[0242] The construction shown in FIG. 25 differs from that shown in FIG.1 as will be described below.

[0243] Referring to FIG. 25, first of all, a plurality of pixelelectrodes PX and a plurality of counter electrodes CT are disposed inthe form of stripes which are extended in parallel with drain signallines DL, and the pixel electrodes PX and the counter electrodes CT areformed to be alternately arranged.

[0244] In Embodiment 4, two pixel electrodes PX and three counterelectrodes CT are disposed, and these two pixel electrodes PX and threecounter electrodes CT are alternately arranged so that two of thecounter electrodes CT are respectively disposed on the opposite extremesides, that is to say, adjacently to the drain signal lines DL.

[0245] The respective counter electrodes CT disposed on the oppositeextreme sides have shielding functions for preventing the pixelelectrodes PX from being influenced by electric fields generated fromthe adjacent drain signal lines DL, and are formed to be wider than theother electrodes.

[0246] The counter electrodes CT are formed at the same time as gatesignal lines GL, and are formed of the same material as the gate signallines GL. Accordingly, the counter electrodes CT are each made of atwo-layer structure having a lower layer formed of an ITO film and anupper layer formed of a Mo layer.

[0247] The three counter electrodes CT are connected in common by beingformed integrally with a counter voltage signal line CL which is formedin parallel with the gate signal lines GL in the central portion of thepixel area. A counter voltage signal is supplied to the counterelectrodes CT via the counter voltage signal line CL. Accordingly, thiscounter voltage signal line CL is also made of a two-layer structurehaving a lower layer formed of an ITO film and an upper layer formed ofa Mo layer.

[0248] This counter voltage signal line CL is formed in common withpixels juxtaposed in the x direction as viewed in FIG. 25, and isconnected in common to the other counter voltage signal lines CL ofpixels arranged in the y direction as viewed in FIG. 25. The countervoltage signal line CL is supplied with the counter voltage signal froma common terminal part CTM which is formed at a common connection lineextended to the outside of a display part.

[0249] The pixel electrodes PX are formed as a layer different from thecounter electrodes CT (the counter voltage signal line CL) with aninsulating film GI interposed between the pixel electrodes PX and thecounter electrodes CT.

[0250] The two pixel electrodes PX are formed in a pattern in which theyare connected to each other over the counter voltage signal line CL. Inthis connection portion, a storage capacitance Cstg which uses theinsulating film GI as its dielectric is formed between the pixelelectrodes PX and the counter voltage signal line CL.

[0251] The one of the two pixel electrodes PX that is closer to the thinfilm transistor TFT is extended at one end to the upper surface of asemiconductor layer AS of the thin film transistor TFT, and constitutesthe source electrode of the thin film transistor TFT.

[0252] This thin film transistor TFT is formed by the resist reflowmethod described previously in, for example, Embodiment 1.

[0253] <<CAPACITANCE ELEMENT Cstg>>

[0254]FIG. 26 is a view showing a cross section of the capacitanceelement Cstg. A part of the pixel electrode PX is superposed on a partof the counter voltage signal line CL with the insulating film GIinterposed therebetween, and the insulating film GI serves as thedielectric film of the capacitance element Cstg.

[0255] Since the pixel electrode PX is formed to be positioned as alayer underlying the protective film PSV, the dielectric film of thecapacitance element Cstg does not use a two-layer structure made of theprotective film PSV and the insulating film GI, and is formed of onlythe insulating film GI.

[0256] For this reason, the capacitance value of the capacitance elementCstg can be set by the film thickness of the insulating film GI and thearea of superposition between the counter voltage signal line CL and thepixel electrode PX, whereby the capacitance value of the capacitanceelement Cstg can readily be set.

[0257] <<COUNTER ELECTRODE CT>>

[0258] Cross sections of the counter electrodes CT are shown in FIG. 27.

[0259] By subjecting each of the counter electrodes CT having thetwo-layer structure to selective etching which allows for the etchingrates of the respective layers, tapered surfaces which become graduallymore open toward the transparent substrate SUB1 can be formed on theside walls of each of the counter electrodes CT, whereby it is possibleto prevent damages such as cracks from occurring in the insulating filmGI at a location where the insulating film GI climbs over any of thecounter electrodes CT, and it is also possible to prevent thedistribution of electric fields between the counter electrodes CT andthe pixel electrodes PX.

[0260] <<DRAIN SIGNAL LINE DL>>

[0261] Cross sections of the drain signal lines DL are shown in FIG. 27.Each of the drain signal lines DL is formed in parallel with the thinfilm transistors TFT formed by a resist reflow method, and is made of astacked structure in which a semiconductor layer AS, ahigh-concentration layer d₀ and a Mo layer d₁ are stacked in that order.Tapered surfaces which become gradually more open toward the transparentsubstrate SUB1 are respectively formed on the side walls of each of thedrain signal lines DL, and steps are respectively formed midway on thesetapered surfaces, specifically, in the portion of the semiconductorlayer AS that underlies the high-concentration layer d₀. Incidentally,the thin film transistors TFT may be formed by the above-describedhalf-exposure method instead of the resist reflow method.

[0262] Therefore, it is possible to fully prevent climb-over damagesfrom occurring in the protective film PSV and the alignment layer ORIwhich are formed to overlie the drain signal lines DL.

[0263] <<GATE TERMINAL PART GTM, COMMON TERMINAL PART CTM>>

[0264] Each gate terminal part GTM has a construction similar to that ofthe gate terminal part GTM described previously in Embodiment 1 (FIG.5). The common terminal part CTM has a two-layer structure formed of thesame material as and in the same layer as the gate signal lines GL, andhas a construction similar to that of the gate terminal part GTM.

[0265] <<DRAIN TERMINAL PART DTM>>

[0266] Each of drain terminal parts DTM has a construction similar tothat of the drain terminal part DTM described previously in Embodiment 1(FIG. 6).

[0267] <<THIN FILM TRANSISTOR TFT>>

[0268] Each of the thin film transistors TFT has a construction similarto that of the thin film transistor TFT described previously inEmbodiment 1 (FIG. 2).

[0269] Embodiment 5.

[0270]FIG. 28 is a plan view showing another embodiment of a pixel onthe in-plane-switching type of liquid crystal display device.

[0271] Referring to FIG. 28, first of all, pixel electrodes PX and acounter electrode CT are respectively formed of transparent conductivelayers such as ITO films, and the counter electrode CT is superposed onthe pixel electrodes PX and is formed in nearly the entire area of thepixel area.

[0272] Specifically, the counter electrode CT is formed on the entirecentral portion of the pixel area except the narrow periphery thereof onthe surface of the transparent substrate SUB1.

[0273] A counter voltage signal is supplied to this counter electrode CTvia a counter voltage signal line CL which is formed to run through thecentral portion of the pixel area in the x direction as viewed in FIG.28.

[0274] The counter voltage signal line CL is formed directly on thecounter electrode CT, and is formed at the same time that the gatesignal lines GL are formed. Accordingly, the counter voltage signal lineCL is made of a two-layer structure having a lower layer formed of anITO film and an upper layer formed of a Mo layer.

[0275] The pixel electrodes PX are formed on an insulating film GI whichcovers the counter electrode CT (the counter voltage signal line CL).The pixel electrodes PX are disposed in, for example, a stripe-shapedpattern which is extended in parallel with drain signal lines DL, andare juxtaposed in a direction perpendicular to the drain signal linesDL.

[0276] The pixel electrodes PX are connected in common at an endconnected to the thin film transistor TFT, and is extended to thesurface of a semiconductor layer AS of the thin film transistor TFT andconstitutes a source electrode SD2 of the thin film transistor TFT.

[0277] This thin film transistor TFT is formed by a resist reflow methodsimilarly to the case of Embodiment 1.

[0278] <<COUNTER ELECTRODE CT>>

[0279] A cross section of the counter voltage signal line CL is shown inFIG. 30.

[0280] By subjecting the counter voltage signal line CL having thetwo-layer structure to selective etching which allows for the etchingrates of the respective layers, tapered surfaces which become graduallymore open toward the transparent substrate SUB1 can be formed on theside walls of the counter voltage signal line CL, whereby it is possibleto prevent climb-over damages occurring in the insulating film GI.

[0281] In addition, since the counter voltage signal line CL is formedon the upper surface of the counter electrode CT made of an ITO film andthe lower layer of the counter voltage signal line CL is made of an ITOfilm, the adhesion of the counter voltage signal line CL to the counterelectrode CT can be ensured.

[0282] <<DRAIN SIGNAL LINE DL>>

[0283] Cross sections of the drain signal lines DL are shown in FIG. 29.Each of the drain signal lines DL is formed in parallel with the thinfilm transistors TFT formed by a resist reflow method, and is made of astacked structure in which the semiconductor layer AS, thehigh-concentration layer d₀ and the Mo layer d₁ are stacked in thatorder. Tapered surfaces which become gradually more open toward thetransparent substrate SUB1 are respectively formed on the side walls ofeach of the drain signal lines DL, and steps are respectively formedmidway on these tapered surfaces, specifically, in the portion of thesemiconductor layer AS that underlies the high-concentration layer d₀.Incidentally, the thin film transistors TFT may be formed by theabove-described half-exposure method instead of the resist reflowmethod.

[0284] Therefore, it is possible to fully prevent climb-over damagesfrom occurring in the protective film PSV and the alignment layer ORIwhich are formed to overlie the drain signal lines DL.

[0285] <<GATE TERMINAL PART GTM, COMMON TERMINAL PART CTM>>

[0286] Each of gate terminal parts GTM and a common terminal part CTMhas a construction similar to that of the gate terminal part GTMdescribed previously in Embodiment 1 (FIG. 5).

[0287] <<DRAIN TERMINAL PART DTM>>

[0288] Each of drain terminal parts DTM has a construction similar tothat of the drain terminal part DTM described previously in Embodiment 1(FIG. 6).

[0289] <<THIN FILM TRANSISTOR TFT>>

[0290] Each of the thin film transistors TFT has a construction similarto that of the thin film transistor TFT described previously inEmbodiment 1 (FIG. 2).

[0291] Embodiment 6.

[0292]FIG. 31 is a plan view showing another embodiment of a pixel onthe in-plane-switching type of liquid crystal display device, andcorresponds to FIG. 25.

[0293]FIG. 31 shows the construction of a pixel formed through ahalf-exposure method. The shown gate signal lines GL has a two-layerstructure made of an ITO film and a Mo layer similarly to the case ofeach of the above-described embodiments, but this construction is notshown in FIG. 31.

[0294] <<STORAGE CAPACITANCE Cstg>>

[0295] A cross section of one of storage capacitances Cstg is shown inFIG. 32.

[0296] The storage capacitance Cstg is formed in such a manner that thepixel electrode PX is superposed on the upper surface of the countervoltage signal line CL with the insulating film GI interposedtherebetween.

[0297] The counter voltage signal line CL has a two-layer structurewhich includes the ITO film g1 as its lower layer and the Mo layer g2 asits upper layer. The pixel electrode PX is made of a stacked structurein which the semiconductor layer AS, the high-concentration layer d₀,the Mo layer d₁ and the ITO film ITO1 are stacked in that order.

[0298] <<PIXEL ELECTRODE PX>>

[0299] Cross sections of the pixel electrodes PX are clearly shown inFIG. 33.

[0300] As described above, each of the pixel electrodes PX is made of astacked structure in which the semiconductor layer AS, thehigh-concentration layer d₀, the Mo layer d₁ and the ITO film ITO1 arestacked in that order.

[0301] In this case, although damages may be caused by steps due to thepixel electrodes PX, the respective side walls of each of the pixelelectrodes PX are formed to have gently tapered surfaces which becomegradually more open toward the transparent substrate SUB1. Accordingly,it is possible to fully mitigate climb-over damages from occurring inthe protective film PSV and the alignment layer ORI which are formed tooverlie the drain signal lines DL.

[0302] <<DRAIN SIGNAL LINE DL>>

[0303] Cross sections of the drain signal lines DL are shown in FIG. 33.

[0304] Each of the drain signal lines DL is also made of a stackedstructure in which the semiconductor layer AS, the high-concentrationlayer d₀, the Mo layer d₁ and the ITO film are stacked in that order,similarly to the case of the pixel electrodes PX.

[0305] For this reason, damages may be caused by steps due to the pixelelectrodes PX, but the respective side walls of each of the drain signallines DL are formed to have gently tapered surfaces which becomegradually more open toward the transparent substrate SUB1, whereby it ispossible to fully mitigate climb-over damages from occurring in theprotective film PSV and the alignment layer ORI which are formed tooverlie the drain signal lines DL.

[0306] <<GATE TERMINAL PART GTM>>

[0307]FIG. 35 is a view showing a cross section of one of gate terminalparts GTM. The shown gate terminal part GTM is formed by openingapertures, respectively, in the protective film PSV and the insulatingfilm GI in that order (by selective etching using dry etching) andexposing an extending end of the gate signal line GL.

[0308] As is apparent from FIG. 35, the gate signal line GL which hasbeen formed of the ITO film g1 as the lower layer and the Mo layer g2 asthe upper layer is formed with the overlying Mo layer g2 being removedat the gate terminal part GTM. This is because the Mo layer g2 for whichno selection ratio can be ensured is etched while the apertures arebeing opened in the protective film PSV and the insulating film GI bydry etching.

[0309] However, the underlying ITO film g1 having the function of astopper of the etching is left, and the function of the gate terminalpart GTM is fully realized by the ITO film g1. In addition, the ITO filmg1 is made of a material which cannot easily be oxidized, whereby it ispossible to form, for example, the gate terminal part GTM havingreliability in resistance to electrolytic corrosion.

[0310] <<DRAIN TERMINAL PART DTM>>

[0311]FIG. 36 is a view showing a cross section of one of drain terminalparts DTM. The shown drain signal line DL is made of a stacked structurein which the semiconductor layer AS, the high-concentration layer d₀,the Mo layer d₁ and the ITO film ITO1 are stacked in that order.Accordingly, the drain terminal part DTM is formed by opening anaperture in the protective film PSV.

[0312] Since the ITO film ITO formed on the surface of the drain signallines DL is exposed by opening the aperture in the protective film PSV,it is not particularly necessary to form an ITO film for preventingelectrolytic corrosion.

[0313] <<THIN FILM TRANSISTOR TFT>>

[0314] In Embodiment 6, the thin film transistors TFT are formed by ahalf-exposure method. FIGS. 37A to 37F are process diagrams showing oneembodiment of a method of forming the above-described thin filmtransistor TFT.

[0315] First, as shown in FIG. 37A, after a gate signal line GL and aninsulating film GI have been formed, a semiconductor layer AS is formedon the surface of this insulating film GI and a high-concentration layerd₀ is formed on the surface of the semiconductor layer AS, and a Molayer d₁ is formed on the high-concentration layer d₀, and furthermore,a ITO film ITO1 is formed on the Mo layer d₁. In this case, thesemiconductor layer AS, the high-concentration layer d₀, the Mo layer d₁and the ITO film ITO1 are continuously deposited in the same chamber.

[0316] As shown in FIG. 37B, a photoresist film PRES is formed on thesurface of the ITO film ITO1, and selective exposure using a photomaskis performed. The photomask used in this case is either a mask having agrid structure or a mask fabricated by controlling the film thickness ofa semi-transparent film such as MoSi, and the photoresist film PRES isleft by using the photomask in portions which correspond to portions inwhich to form a drain signal line DL, a drain electrode SD1 and a sourceelectrode SD2 and in a portion which corresponds to the portion (channelportion) between the drain electrode SD1 and the source electrode SD2.In this case, the film thickness of the photoresist film PRES over thechannel portion is made smaller than the film thickness of thephotoresist film PRES over the other regions.

[0317] Specifically, in the channel portion, resist conditions arecontrolled so that the time of completion of etching of the photoresist,the Mo layer d₁ and the high-concentration layer d₀ becomes(approximately) the same as the time of completion of etching of the Molayer d₁, the high-concentration layer d₀ and the semiconductor layerAS.

[0318] As shown in FIG. 37C, the photoresist film PRES is used a mask,and the portions of the ITO film ITO1, the Mo layer d₁, thehigh-concentration layer d₀ and the semiconductor layer AS that areexposed from this mask are selectively etched (for example, afluorine-containing gas such as SF₆ or CF₄ is selected as a gas forselective etching of the semiconductor layer AS and thehigh-concentration layer d₀).

[0319] In this manner, the semiconductor layer AS which constitutes thethin film transistor TFT is etched in an island-like shape, but thechannel portion is etched to at least the high-concentration layer d₀.After that, the photoresist film PRES is removed.

[0320] As shown in FIG. 37D, a protective film PSV is formed. As shownin FIG. 37E, a photoresist film PRES is formed on the surface of theprotective film PSV so that an aperture is formed in the central portionof the pixel area (including the region in which the thin filmtransistor TFT is formed) except the periphery of the pixel area.

[0321] As shown in FIG. 37F, this photoresist film PRES is used as amask to remove the portion of the protective film PSV that is exposedfrom this mask. Incidentally, at the same time that holes are formed inthis protective film PSV, holes at the gate terminal parts GTM and thedrain terminal parts DTM are also formed. After that, the photoresistfilm PRES is removed.

[0322] <<MANUFACTURING METHOD>>

[0323]FIGS. 38A to 38E are process diagrams showing one embodiment of amanufacturing method for the above-described liquid crystal displaydevice. FIGS. 38A to 38E are views showing the process diagrams forforming the portion of the gate terminal part GTM, together with theprocess diagrams shown in FIGS. 37A to 37F. FIG. 38A corresponds to FIG.37B, FIG. 38C corresponds to FIG. 37C, FIG. 38D corresponds to FIG. 37E,and FIG. 38E corresponds to FIG. 37F.

[0324] A series of processes is as shown in the Table of FIG. 39. As isapparent from this table, the number of photo-processes can be reducedto three, specifically, the patterning of the gate signal lines GL, thepatterning of the drain signal lines DL (the drain electrodes and thesource electrodes), and the pattering of the protective film PSV.

[0325] Embodiment 7.

[0326]FIG. 40 is a plan view showing another embodiment of a pixel onthe liquid crystal display device according to the invention, andcorresponds to FIG. 28. Specifically, a counter electrode CT made of,for example, an ITO film is formed in the greater part of the pixelarea, and a plurality of pixel electrodes PX made of, for example, anITO film are formed to be juxtaposed in the form of stripes. InEmbodiment 7, the insulating film interposed between the counterelectrode CT and the pixel electrodes PX has a two-layer structure madeof an insulating film GI and a protective film PSV. A film transistorTFT is formed by a resist reflow method.

[0327] Incidentally, FIG. 41 shows a cross-sectional view taken alongline 41-41 of FIG. 40, FIG. 42 shows a cross-sectional view taken alongline 44-44 of FIG. 40, and FIG. 45 shows a cross-sectional view takenalong line 45-45 of FIG. 40.

[0328] <<DRAIN SIGNAL LINE DL>>

[0329] Cross sections of drain signal lines DL are shown in FIG. 41.Each of the drain signal lines DL is formed on the insulating film GI,and is made of a stacked structure in which the semiconductor layer AS,the high-concentration layer d₀ and the Mo layer d₁ are stacked in thatorder.

[0330] Since the drain signal lines DL are formed in parallel with thethin film transistors TFT formed by the resist reflow method, the sidewalls of each of the drain signal lines DL are respectively formed tohave gently tapered surfaces (which become gradually more open towardthe transparent substrate SUB1) with steps being respectively formed onthe opposite side surfaces of the semiconductor layer AS of each of thedrain signal lines DL.

[0331] <<GATE SIGNAL LINE GL>>

[0332] Cross sections of gate signal lines GL are shown in FIG. 42. Eachof the gate signal lines GL is formed on the transparent substrate SUB1,and is made of a stacked structure in which the ITO film g1 and the Molayer g2 are stacked in that order. Tapered surfaces which becomegradually more open toward the transparent substrate SUB1 arerespectively formed on the side walls of each of the gate signal linesGL.

[0333] <<COUNTER VOLTAGE SIGNAL LINE CL>>

[0334] A cross section of a counter voltage signal line CL is shown inFIG. 42. The counter voltage signal line CL is made of a stackedstructure in which the ITO film g1 and the Mo layer g2 are stacked inthat order, similarly to the gate signal lines GL. The ITO film g1 isformed to be wider than the Mo layer g2 so that the ITO film g1 canserve the function of the counter electrode CT.

[0335] As described above, although the counter electrode CT has aone-layer structure, the counter voltage signal line CL has a two-layerstructure in which a layer made of a material different from that of thecounter electrode CT is formed on a layer which constitutes the counterelectrode CT. The counter voltage signal line CL and the counterelectrode CT can be formed by one photo-process adopting a half-exposuremethod.

[0336]FIGS. 43A to 43D are views showing a process to be used in thiscase. First of all, as shown in FIG. 43A, a stacked structure in which,for example, the ITO film g1 and the Mo layer g2 are stacked in thatorder is formed on the surface of the transparent substrate SUB1.

[0337] Then, a photoresist film PRES is selectively formed on thesurface of the stacked structure, but as shown in FIG. 43B, thephotoresist film PRES has different thicknesses in different areas. Theformation of the photoresist film having different thicknesses isachieved by effecting so-called half-exposure using either a photomaskhaving a grid structure or a photomask fabricated by controlling thefilm thickness of a semi-transparent film such as MoSi.

[0338] After that, as shown in FIG. 43C, the overlying Mo layer g2 isselectively etched by using the photoresist film PRES as a mask. In thiscase, the photoresist film of larger film thickness is left in the formof a photoresist film of reduced film thickness, but the photoresistfilm of smaller film thickness vanishes.

[0339] Then, as shown in FIG. 43D, the underlying ITO film g1 isselectively etched by using the remaining photoresist film PRES as amask. In this case, the Mo layer g2 lying on the side where thephotoresist film is vanished is etched at this time.

[0340] <<GATE TERMINAL PART GTM>>

[0341] A cross section of one of gate terminal parts GTM is shown inFIG. 44. The shown gate terminal part GTM is formed by opening anaperture in the insulating film GI and the protective film PSV whichcovers the gate signal lines GL.

[0342] In this case, the Mo layer g2 which is the upper layer of thegate signal lines GL is removed by opening the aperture, and theelectrolytic corrosion of the gate terminal part GTM can be far moreeffectively prevented by an ITO film which is formed in the aperture aswell as in a portion around the aperture. Incidentally, the ITO film isformed at the same time as the pixel electrodes PX.

[0343] <<DRAIN TERMINAL PART DTM>>

[0344] A cross section of one of drain terminal parts DTM is shown inFIG. 45. The drain terminal part DTM is formed by opening an aperture inthe protective film PSV which covers the drain signal lines DL.

[0345] In this case, the electrolytic corrosion of the gate terminalpart GTM can be far more effectively prevented by an ITO film which isformed in the aperture as well as in a portion around the aperture. ThisITO film is also formed at the same time as the pixel electrodes PX.

[0346] <<MANUFACTURING METHOD>>

[0347]FIGS. 46A to 46D, FIGS. 47E to 47H and FIG. 48I are processdiagrams showing one embodiment of a manufacturing method for theabove-described liquid crystal display device, and show a portion whichincludes a thin film transistor TFT and a counter electrode CT.

[0348] First of all, as shown in FIG. 46A, after a gate signal line GLand an insulating film GI have been formed, a semiconductor layer AS, ahigh-concentration layer d₀ and a Mo layer d₁ are formed on the surfaceof the insulating film GI in a stacked manner. In this case, thesemiconductor layer AS, the high-concentration layer d₀ and the Mo layerd₁ are continuously deposited in the same chamber.

[0349] As shown in FIG. 46B, a photoresist film PRES is formed on thesurface of an ITO film, and selective exposure using a photomask isperformed. The photomask used in this case is either a mask having agrid structure or a mask fabricated by controlling the film thickness ofa semi-transparent film such as MoSi, and the photoresist film PRES isleft by using the photomask in portions which correspond to portions inwhich to form a drain signal line DL, a drain electrode SD1 and a sourceelectrode SD2 and in a portion which corresponds to the portion (channelportion) between the drain electrode SD1 and the source electrode SD2.In this case, the film thickness of the photoresist film PRES over thechannel portion is made smaller than the film thickness of thephotoresist film PRES over the other regions.

[0350] Specifically, in the channel portion, resist conditions arecontrolled so that the time of completion of etching of the photoresist,the Mo layer d₁ and the high-concentration layer d₀ becomes(approximately) the same as the time of completion of etching of the Molayer d₁, the high-concentration layer d₀ and the semiconductor layerAS.

[0351] As shown in FIG. 46C, the photoresist film PRES is used a mask,and the portions of the Mo layer d₁, the high-concentration layer d₀ andthe semiconductor layer AS that are exposed from this mask areselectively etched (for example, a fluorine-containing gas such as SF₆or CF₄ is selected as a gas for selective etching of the semiconductorlayer AS and the high-concentration layer d₀).

[0352] In this manner, the semiconductor layer AS is exposed in the areaother than the area in which to form the thin film transistor TFT, andthe photoresist film PRES is reduced in film thickness in its entirearea. In the channel portion, the Mo layer d₁ is exposed from thephotoresist film PRES.

[0353] As shown in FIG. 46D, etching is performed by using the remainingphotoresist film PRES as a mask. In this manner, the semiconductor layerAS is exposed in the area other than the area in which to form the thinfilm transistor TFT, and the insulating film GI is exposed.

[0354] In addition, in the channel portion, the Mo layer d₁ and thehigh-concentration layer d₀ are etched, and the semiconductor layer ASis exposed. As shown in FIG. 47E, a protective film PSV is formed.

[0355] As shown in FIG. 47F, a photoresist film PRES is formed on theupper surface of the protective film PSV so that an aperture is formedin a portion in which to form a contact hole for the source electrodeSD2 of the thin film transistor TFT. Then, the protective film PSV isetched by using the photoresist film PRES as a mask. Incidentally, atthe same time that holes are formed in this protective film PSV, holesat the gate terminal parts GTM and the drain terminal parts DTM are alsoformed. After that, the photoresist film PRES is removed.

[0356] As shown in FIG. 47G, the contact hole is formed in theprotective film PSV, and a part of the source electrode SD2 of the thinfilm transistor TFT is exposed from this contact hole. As shown in FIG.47H, an ITO film is formed on the protective film PSV, and a photoresistfilm PRES is formed on the ITO film over an area in which to form apixel electrodes PX and an extending portion of the pixel electrodes PXto be connected to the source electrode SD2 of the thin film transistorTFT. As shown in FIG. 48I, the ITO film is etched by using thephotoresist film PRES as a mask, and then the photoresist film PRES isremoved.

[0357] Embodiment 8.

[0358]FIG. 49 is a plan view showing another embodiment of a pixel onthe liquid crystal display device according to the invention, andcorresponds to FIG. 40. The construction shown in FIG. 49 differs fromthat shown in FIG. 40 in that a resist reflow method is adopted and nocontact holes are formed in the protective film PSV. Incidentally, FIG.50 shows a cross section taken along line 50-50 of FIG. 49, and FIG. 51shows a cross section taken along line 51-51 of FIG. 49.

[0359] <<DRAIN SIGNAL LINE DL>>

[0360] Cross sections of drain signal lines DL are shown in FIG. 50.Each of the drain signal lines DL is made of a stacked structure inwhich a semiconductor layer AS, a high-concentration layer d₀, a Molayer d₁ and an ITO film ITO1 are stacked in that order. In thisconstruction, the ITO film ITO1 is formed to be extended to the sidewalls of the stacked structure, that is to say, to cover the whole ofthe drain signal line DL.

[0361] <<GATE SIGNAL LINE GL>>

[0362] Cross sections of gate signal lines GL are shown in FIG. 51. Eachof the gate signal lines GL is formed on the transparent substrate SUB1,and is made of a stacked structure in which the ITO film g1 and the Molayer g2 are stacked in that order. Tapered surfaces which becomegradually more open toward the transparent substrate SUB1 arerespectively formed on the side walls of each of the gate signal linesGL.

[0363] <<COUNTER VOLTAGE SIGNAL LINE CL>>

[0364] A cross section of a counter voltage signal line CL is shown inFIG. 51. The counter voltage signal line CL is made of a stackedstructure in which the ITO film g1 and the Mo layer g2 are stacked inthat order, similarly to the gate signal lines GL. The ITO film g1 isformed to be wider than the Mo layer g2 so that the ITO film g1 canserve the function of the counter electrode CT.

[0365] <<DRAIN TERMINAL PART DTM>>

[0366] A cross section of one of drain terminal parts DTM is shown inFIG. 52. The drain terminal part DTM is made of a stacked structure inwhich the semiconductor layer AS, the high-concentration layer d₀, theMo layer d₁ and the ITO film ITO1 are stacked in that order. In thisconstruction, the ITO film ITO1 is formed to be extended to the sidewalls of the stacked structure.

[0367] The drain terminal part DTM is formed by opening apertures in theprotective film PSV which covers the drain signal lines DL and exposingthe surface of the ITO film.

[0368] <<MANUFACTURING METHOD>>

[0369]FIGS. 53A to 53D are process diagrams showing one embodiment of amanufacturing method for the above-described liquid crystal displaydevice, and show a portion which includes a thin film transistor TFT anda counter electrode CT.

[0370] First of all, as shown in FIG. 53A, after a gate signal line GL,the counter electrode CT and a counter voltage signal line CL have beenformed on the surface of the transparent substrate SUB1, an insulatingfilm GI is formed to cover the gate signal line GL, the counterelectrode CT and the counter voltage signal line CL.

[0371] A semiconductor layer AS, a high-concentration layer d₀ and a Molayer d₁ are formed on the surface of the insulating film GI in astacked manner, whereby the thin film transistor TFT and a drain signallines DL are formed by the above-described resist reflow method.

[0372] An ITO film ITO1 is formed on the entire area of the surface ofthe transparent substrate SUB1 formed in this manner, and a photoresistfilm PRES is formed on the surface of the ITO film ITO1 in a portionwhich corresponds to an area in which to form a pixel electrodes PX.

[0373] Then, the ITO film ITO1 is etched by using this photoresist filmPRES as a mask, whereby the pixel electrodes PX is formed as shown inFIG. 53B. As shown in FIG. 53C, a protective film PSV is formed.

[0374] Then, as shown in FIG. 53D, an aperture is opened in theprotective film PSV through a photo-process (not shown), therebypreparing a construction in which the protective film PSV is not formedin the central portion of the pixel area except the periphery thereof.Incidentally, at the same time that holes are formed in this protectivefilm PSV, holes at the gate terminal parts GTM and the drain terminalparts DTM are also formed.

[0375] Incidentally, in each of the above-described embodiments, the Molayer d₁ which constitutes the drain signal lines DL, the drainelectrodes SD1 and the source electrodes SD2 are formed of molybdenum(Mo), but even if molybdenum (Mo) is replaced with another high meltingpoint metal such as tungsten (W), chromium (Cr), titanium (Ti) ortantalum (Ta), it is possible to achieve similar advantages.

[0376] In addition, an IZO (Indium-Zinc-Oxide) film may also be usedinstead of each of the above-described ITO films. As is apparent fromthe foregoing description, in accordance with the liquid crystal displaydevice according to the invention, it is possible to obtain aconstruction in which signal lines have small wiring resistivity.

[0377] In addition, in accordance with the liquid crystal display deviceaccording to the invention, it is possible to obtain a construction inwhich few steep steps are present on the liquid-crystal-side surface ofa substrate. In addition, in accordance with the manufacturing methodfor the liquid crystal display device according to the invention, it ispossible to reduce the number of processes in the manufacturing method.

What is claimed is:
 1. A liquid crystal display device comprising:substrates disposed in opposition to each other with a liquid crystalinterposed therebetween; a thin film transistor to be driven by ascanning signal supplied from a gate signal line; and a pixel electrodeto be supplied with a video signal from a drain signal line via the thinfilm transistor, the thin film transistor and the pixel being providedin each pixel area on a liquid-crystal-side surface of one of thesubstrates, the gate signal line being made of a multi-layered structureincluding: either one of an ITO film and an IZO film which is formed onat least the liquid-crystal-side surface; and a layer formed to overliethe either one of the ITO film and the IZO film, the layer being any oneof a Mo layer, a W layer, a Cr layer, a Ti layer and a Ta layer, or analloy layer made of arbitrary ones of Mo, W, Cr, Ti and Ta.
 2. A liquidcrystal display device comprising: substrates disposed in opposition toeach other with a liquid crystal interposed therebetween; a thin filmtransistor to be driven by a scanning signal supplied from a gate signalline; and a pixel electrode to be supplied with a video signal from adrain signal line via the thin film transistor, the thin film transistorand the pixel being provided in each pixel area on a liquid-crystal-sidesurface of one of the substrates, the gate signal line being made of amulti-layered structure including: either one of an ITO film and an IZOfilm which is formed on at least the liquid-crystal-side surface; and alayer formed to overlie the either one of the ITO film and the IZO film,the layer being any one of a Mo layer, a W layer, a Cr layer, a Ti layerand a Ta layer, or an alloy layer made of arbitrary ones of Mo, W, Cr,Ti and Ta, the pixel electrode being formed on an insulating film whichincludes as one area a gate insulating film of the thin film transistor.3. A liquid crystal display device according to claim 2, wherein thethin film transistor is made of a stacked structure in which a gateelectrode connected to the gate signal line, the gate insulating film, asemiconductor layer and a pair of electrodes formed on the upper surfaceof the semiconductor layer are stacked in that order, an extended end ofthe pixel electrode being formed on the upper surface of thesemiconductor layer to constitute one of the pair of electrodes.
 4. Amanufacturing method for a liquid crystal display device comprising thesteps of: forming, on a substrate, gate signal lines each made of astacked structure in which a transparent conductive film and a metallayer are stacked in that order; forming an insulating film to cover thegate signal lines; forming, on the insulating film, a stacked structurein which a semiconductor layer, a high-concentration layer and aconductive layer are stacked in that order; performing selective etchingof the conductive layer and the high-concentration layer by using aresist reflow method, to form drain electrodes and source electrodes forthin film transistors as well as drain signal lines and to performselective etching of the semiconductor layer; forming pixel electrodeseach of which is in part directly superposed on the source electrode ofthe corresponding one of the thin film transistors; and forming aprotective film and opening, in the protective film, apertures forexposing the respective pixel electrodes.
 5. A manufacturing method fora liquid crystal display device according to claim 4, wherein the resistreflow method includes the steps of: forming a photoresist film on anarea in which to form the drain electrode and the source electrode ofeach of the thin film transistors as well as the corresponding one ofthe drain signal lines; performing etching using the photoresist film asa mask; sagging the photoresist film to cause the photoresist film toexist at least between the drain electrode and the source electrode; andperforming etching using the sagged photoresist film as a mask.
 6. Aliquid crystal display device according to claim 4, wherein at the sametime that the pixel electrodes are formed, a transparent conductive filmis deposited on areas in which to form drain terminal parts of therespective drain signal lines.
 7. A liquid crystal display deviceaccording to claim 4, wherein at the same time that holes are opened inthe protective film, holes at gate terminal parts and drain terminalparts are opened.
 8. A manufacturing method for a liquid crystal displaydevice comprising the steps of: forming, on a substrate, gate signallines each made of a stacked structure in which a transparent conductivefilm and a metal layer are stacked in that order; forming an insulatingfilm to cover the gate signal lines; forming, on the insulating film, astacked structure in which a semiconductor layer, a high-concentrationlayer and a conductive layer are stacked in that order; performingselective etching of the conductive layer and the high-concentrationlayer by using a half-exposure method, to form drain electrodes andsource electrodes for thin film transistors as well as drain signallines and to perform selective etching of the semiconductor layer;forming pixel electrodes each of which is in part directly superposed onthe source electrode of the corresponding one of the thin filmtransistors; and forming a protective film and opening, in theprotective film, apertures for exposing the respective pixel electrodes.9. A manufacturing method for a liquid crystal display device accordingto claim 8, wherein the half-exposure method includes the steps of:forming a photoresist film of larger film thickness on an area in whichto form the drain electrode and the source electrode of each of the thinfilm transistors as well as the corresponding one of the drain signallines, and a protective film of smaller film thickness on an areabetween the drain electrode and the source electrode; and performingetching using the photoresist film as a mask.
 10. A manufacturing methodfor a liquid crystal display device according to claim 8, wherein at thesame time that the pixel electrodes are formed, a transparent conductivefilm is deposited on areas in which to form drain terminal parts of therespective drain signal lines.
 11. A liquid crystal display deviceaccording to claim 8, wherein at the same time that holes are opened inthe protective film, holes at gate terminal parts and drain terminalparts are opened.
 12. A manufacturing method for a liquid crystaldisplay device comprising the steps of: forming, on a substrate, gatesignal lines each made of a stacked structure in which a transparentconductive film and a metal layer are stacked in that order; forming aninsulating film to cover the gate signal lines; forming, on theinsulating film, a stacked structure in which a semiconductor layer, ahigh-concentration layer and a conductive layer are stacked in thatorder; performing selective etching so that the conductive layer, thehigh-concentration layer and the semiconductor layer are left in each ofan area in which to form drain electrodes for thin film transistors, anarea in which to form source electrodes for the thin film transistors,an area between the drain electrode and the source electrode of each ofthe thin film transistors, and an area in which to form drain signallines; forming a transparent conductive film which constitutes pixelelectrodes; performing selective etching so that the transparentconductive film is left in each of the area in which to form the drainelectrodes for the thin film transistors, the area in which to form thesource electrodes for the thin film transistors, the area in which toform the drain signal lines, and an area in which to form the pixelelectrodes; performing selective etching of the conductive layer and thehigh-concentration layer between the drain electrode and the sourceelectrode of each of the thin film transistors by using the remainingtransparent film as a mask; and forming a protective film and opening,in the protective film, apertures for exposing the respective pixelelectrodes.
 13. A manufacturing method for a liquid crystal displaydevice according to claim 12, wherein at the same time that holes areopened in the protective film, holes at gate terminal parts and drainterminal parts are opened.
 14. A manufacturing method for a liquidcrystal display device comprising the steps of: forming, on a substrate,a transparent conductive film and a conductive layer partly superposedon the transparent conductive film, and forming counter electrodes froma single layer made of the transparent conductive film, as well as gatesignal lines and counter voltage signal lines from a stacked structurein which the transparent conductive film and the conductive layer arestacked; forming an insulating film to cover the counter electrodeelectrodes, the counter voltage signal lines and the gate signal lines;forming, on the insulating film, a stacked structure in which asemiconductor layer, a high-concentration layer and a conductive layerare stacked in that order; performing selective etching of theconductive layer and the high-concentration layer by using a resistreflow method, to form drain electrodes and source electrodes for thinfilm transistors as well as drain signal lines and to perform selectiveetching of the semiconductor layer; forming pixel electrodes each madeof a transparent conductive film which is in part directly superposed onthe source electrode of the corresponding one of the thin filmtransistors; and forming a protective film and opening, in theprotective film, apertures for exposing the respective pixel electrodes.15. A manufacturing method for a liquid crystal display device accordingto claim 14, wherein the resist reflow method includes the steps of:forming a photoresist film on an area in which to form the drainelectrode and the source electrode of each of the thin film transistorsas well as the corresponding one of the drain signal lines; performingetching using the photoresist film as a mask; sagging the photoresistfilm to cause the photoresist film to exist at least between the drainelectrode and the source electrode; and performing etching using thesagged photoresist film as a mask.
 16. A liquid crystal display deviceaccording to claim 14, wherein at the same time that the pixelelectrodes are formed, a transparent conductive film is deposited onareas in which to form drain terminal parts of the respective drainsignal lines.
 17. A liquid crystal display device according to claim 14,wherein at the same time that holes are opened in the protective film,holes at gate terminal parts and drain terminal parts are opened.
 18. Amanufacturing method for a liquid crystal display device comprising thesteps of: forming, on a substrate, a transparent conductive film and aconductive layer partly superposed on the transparent conductive film,and forming counter electrodes from a single layer made of thetransparent conductive film, as well as gate signal lines and countervoltage signal lines from a stacked structure in which the transparentconductive film and the conductive layer are stacked; forming aninsulating film to cover the counter electrode electrodes, the countervoltage signal lines and the gate signal lines; forming, on theinsulating film, a stacked structure in which a semiconductor layer, ahigh-concentration layer and a conductive layer are stacked in thatorder; performing selective etching of the conductive layer and thehigh-concentration layer by using a half-exposure method, to form drainelectrodes and source electrodes for thin film transistors as well asdrain signal lines and to perform selective etching of the semiconductorlayer; forming pixel electrodes each made of a transparent conductivefilm which is in part directly superposed on the source electrode of thecorresponding one of the thin film transistors; and forming a protectivefilm and opening, in the protective film, apertures for exposing therespective pixel electrodes.
 19. A manufacturing method for a liquidcrystal display device according to claim 18, wherein the half-exposuremethod includes the steps of: forming a photoresist film of larger filmthickness on an area in which to form the drain electrode and the sourceelectrode of each of the thin film transistors as well as thecorresponding one of the drain signal lines, and a protective film ofsmaller film thickness on an area between the drain electrode and thesource electrode; and performing etching using the photoresist film as amask.
 20. A manufacturing method for a liquid crystal display deviceaccording to claim 18, wherein at the same time that the pixelelectrodes are formed, a transparent conductive film is deposited onareas in which to form drain terminal parts of the respective drainsignal lines.
 21. A liquid crystal display device according to claim 18,wherein at the same time that holes are opened in the protective film,holes at gate terminal parts and drain terminal parts are opened.
 22. Amanufacturing method for a liquid crystal display device comprising thesteps of: forming on a substrate a stacked structure in which a firstmaterial layer and a second material layer are stacked in that order;forming a photoresist film on the upper surface of the stacked structureand forming a photoresist film of larger film thickness on a first areaas well as a photoresist film of smaller film thickness on a second areaby using half exposure; etching the second material layer by using thephotoresist film as a mask and vanishing the photoresist film of smallerfilm thickness; etching the first material layer by using the secondmaterial layer as a mask; and forming a stacked structure in which thefirst material layer and the second material layer are stacked in thatorder on the first area of the substrate, and forming the first materiallayer on the second area.
 23. A manufacturing method for a liquidcrystal display device which includes pixel areas provided on aliquid-crystal-side surface of either one of substrates disposed inopposition to each other with a liquid crystal interposed therebetween,each of the pixel areas being surrounded by gate signal lines disposedto be extended in the x direction and to be juxtaposed in the ydirection and drain signal lines disposed to be extended in the ydirection and to be juxtaposed in the x direction; each of the pixelareas including: a switching element to be driven by a gate signal fromeither one of the gate signal lines; a pixel electrode to be suppliedwith a video signal from a drain signal line via the switching element;and a counter electrode for causing an electric field to be generatedbetween the counter electrode and the pixel electrode, the manufacturingmethod comprising the steps of: forming, on either one of thesubstrates, a stacked structure in which a first material layer and asecond material layer are stacked in that order; forming a photoresistfilm on the upper surface of the stacked structure and forming, by usinghalf exposure, a photoresist film of larger film thickness on each areain which to form a gate signal line as well as a photoresist film ofsmaller film thickness on each area in which to form a counterelectrode; etching the second material layer by using the photoresistfilm as a mask and vanishing the photoresist film of smaller filmthickness; and etching the first material layer by using the secondmaterial layer as a mask.
 24. A manufacturing method for a liquidcrystal display device according to claim 21 or 23, wherein the firstmaterial layer is made of an ITO film, and the second material layer ismade of a Mo layer.